The present invention relates to fabrication of infrared imagers.
It is highly desirable to have infrared imagers which will operate at wavelengths down to the limits of the available long-wavelength atmospheric window, i.e. at wavelengths of 8-12 microns.
The detection of such long wavelengths, if it is to be done at moderate cryogenic temperatures (e.g. at liquid nitrogen rather than liquid helium temperatures), is preferably done using a very narrow bandgap semiconductor, such as Hg.sub.l-x Cd.sub.x Te. Such alloys are referred to generically as "HgCdTe". This pseudo-binary alloy, if it has a composition such as x=0.2, will have a bandgap small enough (0.1 eV) to be bridged by 12 micron photons.
Conventional approaches using HgCdTe area arrays have typically used HgCdTe photodiodes as optical detectors, and have interconnected these photodiodes with silicon processing stages.
However, if any sizable array of infrared detectors is used, it can be a very difficult problem to get the raw output of the infrared detectors over to the silicon processor stages. That is, there are many applications for which a two-dimentional focal plane array larger then 100.times.100 would be desirable. In such applications, it is very difficult to connect so many infrared detector locations to silicon processing stages without greatly degrading the duty cycle of the detector stages. In particular, where photo-diode detector cells are used, the silicon processing circuitry required is rather complex, and a merely reasonable pitch in the infrared imaging plane (e.g. 0.002" pixel spacing center-to-center) would impose stringent requirements on silicon geometry, if the same pitch must be followed in the silicon processing stages.
One method which has been used in the prior art to connect infrared detector sites to silicon processors is a hybrid approach, in which the infrared detector cells are bump bonded, in many separate operations, onto a silicon carrier. This is an expensive low-yield operation.
Thus it is an object of the present invention to provide an infrared imager process which permits direct connection from an infrared detection site to silicon processing stages.
Prior art method for interconnection of HgCdTe to silicon substrates has been bump bonding. In this method, a tall host of a metal such as indium which is very soft at room temperatures is formed at each pixel site in the HgCdTe, and the HgCdTe is flipped over and pressed onto the silicon so that the indium bump bonding posts provide deformable contacts to a pattern of bonding sites on the silicon.
However, this approach has several difficulties. First, it requires that the detector technology used to be such that the HgCdTe detector cells can be accessed from the backside of the chip. Second, it requires a mechanical pressure-bonding step which may induce damage. Third, the unusaul processing step required to form the indium posts will itself make some contribution to yield degradation. Fourth, the alignment step which aligns the indium posts on the under side of the HgCdTe slice with the contact locations on the silicon surface can be rather difficult.
An alternative method of vertically integrating HgCdTe with silicon would be to cut vias through the HgCdTe, so that contact could h=made from the front surface of the HgCdTe to silicon contacts. However, while processes which will cut vias through HgCdTe are known, there are significant difficulties with the prior art processes. First, it is very important that the HgCdTe via be formed without inducing physical damage or surface states beyond an absolute minimum. Since the bandgap of HgCdTe is so small, it does not take much physical damage to induce disastrous leakage current levels or disastrously lowered breakdown voltages. One aspect of this requirement is the walls of the HgCdTe via should be extremely smooth. However, this has been difficult to achieve with prior art methods. Second, in order to achieve good quality deposition of insulator and metal layers through the via hole, it is desirable to be able to control the taper of the via hole, i.e., the slope of the sidewalls. This is also difficult with the prior art methods. Moreover, it may be necessary to precisely control via size in HgCdTe. Thus, for example, if the via protrudes into an active region of the infrared detection device, i.e., into a region where photo carriers are being generated and collected, the via walls may provide a leakage path which partially shorts out the detection device. Alternatively, if the via is undersized, the contact made to silicon may not be of adequate quality.
Thus, it is an object of the present invention to provide a method for cutting via holes through HgCdTe.
It is a further object of the present invention to provide a method for cutting via holes through HgCdTe which have controlled sidewall slope.
It is a further object of the present invention to provide a method for cutting via holes through HgCdTe which have very smooth sidewalls.
It is a further object of the present invention to provide a method for cutting via holes through HgCdTe wherein the via sidewalls have a minimal density of recombination sites.
It is a further object of the present invention to provide a method for cutting via holes through HgCdTe wherein the sidewall slope and the size of the via are both precisely controlled.
To achieve these and other objects of the invention, the present invention provides:
A method for etching vias in HgCdTe, comprising the steps of:
ion milling a hole through said HgCdTe, said hole being substantially smaller than the desired diameter of said via; and
Spray etching said HgCdTe, whereby said hole is enlarged to form a via having a desired size and smooth walls.